1. Field of Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a non-volatile memory and a fabricating method thereof.
2. Description of Related Art
The electrically erasable programmable read only memory (EEPROM) possesses the ability to store, read and erase data for several times. Moreover, the EEPROM has the advantage that the stored data is not lost even after the system is power off. Therefore, the EEPROMs are widely used in the personal computers and electronic equipments.
Typical EEPROM is composed of a floating gate and a control gate, which are made of doped polysilicon. When the memory is programmed, the electrons injected into the floating gate uniformly distributes in the polysilicon floating gate layer. However, when there are defects in the tunnel oxide layer under the polysilicon floating gate layer, the leakage is easily produced in the device. Hence, the reliability of the device is decreased.
Currently, in order to solve the leakage problem of the EEPROM, a charge storage layer is used to substitute the polysilicon floating gate. The charge storage layer is made of silicon nitride. Usually, each side of the silicon nitride charge storage layer has a silicon oxide layer so as to form a stacked gate structure including a silicon oxide/silicon nitride/silicon oxide (ONO) complex dielectric layer.
In addition, another advantage obtained from replacing the polysilicon floating gate with the silicon nitride layer is that the electrons are only stored in a portion of the silicon nitride layer over the channel region adjacent to the source region or drain region while the device is programmed. Therefore, during the programming process, the voltages can be applied on the source region and the control gate respectively. Hence, the electrons are stored in a portion of the silicon nitride layer near the drain region with a form of Gaussian distribution. Alternatively, the voltages can be applied on the drain region and the control gate respectively. Hence, the electrons are stored in a portion of the silicon nitride layer near the source region with a form of Gaussian distribution. On the other words, there are two storage regions in a single silicon nitride layer. By properly applying the voltages on the control gate and on either the source region or the drain region, there can be four different storage states, which includes each of the storage regions having one group of electrons with a Gaussian distribution property, either one of the storage regions having one group of electrons with a Gaussian distribution property and none of the electrons stored in both storage regions, in a single silicon nitride layer. That is, a single flash memory cell can present four different storage states. Hence, instead of using the floating gate, the flash memory with a silicon nitride charge storage layer is considered a 2-bit-per-cell memory.
Conventionally, in order to increase the number of bits of a unit cell, a memory structure with a vertical memory cell is developed. This kind of memory cell is a 4-bit-per-cell flash memory. However, between two vertical memory cells, the phenomenon of electron punching through happens easily. Hence, the leakage in the memory structure is induced.